CSCE 313 - Exam I
CSCE 313
CSCE 313
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After handling a fault successfully, the CPU
goes (when it does go back) to the instruction
immediately after the faulting one.
Interrupts are asynchronous events.
Memory limit protection (within a private
address space using base and bound) is
implemented in the hardware instead of
software.
Memory limit protection checks are only
performed in the User mode
Translation Look-aside Buffer (TLB) is a
cache for popular (i.e., recently used) page
table entries.
Divide by 0 is an example of a fault.
Every process has its own page table.
A process cannot access its own page table.
