CSCE 313 - Exam I
CSCE 313
CSCE 313
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| Kategorie | Informatik |
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| Erstellt / Aktualisiert | 23.02.2020 / 24.02.2020 |
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After handling a fault successfully, the CPU
goes (when it does go back) to the instruction
immediately after the faulting one.
Interrupts are asynchronous events.
Memory limit protection (within a private
address space using base and bound) is
implemented in the hardware instead of
software.
Memory limit protection checks are only
performed in the User mode
Translation Look-aside Buffer (TLB) is a
cache for popular (i.e., recently used) page
table entries.
Divide by 0 is an example of a fault.
Every process has its own page table.
A process cannot access its own page table.
Trap is a type of synchronous exception.
Faults are unintentional but possibly
recoverable.
Which of the following are privileged operations
allowed only in Kernel mode?
Which of the following are privileged operations
allowed only in Kernel mode?
Why is the process state
(i.e., PC, SP, EFLAGS, general registers)
kept in the Kernel
Interrupt Stack before handling an Interrupt?
Why could we not store it in the user memory?
What is the risk?
If the process is buggy or points to an invalid
memory address, the kernel needs to still
function properly.
It is not run on User memory, that way there is
always a dedicated amount of memory used for
OS operations, in case the user memory is filled
up with other processes.
