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Subhan Waizi
Karten 38 Karten
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Erstellt / Aktualisiert 12.05.2016 / 16.06.2017
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0 Exakte Antworten 38 Text Antworten 0 Multiple Choice Antworten
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Draw the block diagram of a single-bit adder.

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See figure.

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What are the ARMv7 architecture profiles?

  • Applicatoin profile (ARMv7-A)
    • memory management support (MMU)
    • highest performance at low power suited for multi-tasking OS requirements
    • TrustZone and Jacelle-RCT for a safe and extensible system
    • for example CortexA5, Cortex-A9
  • Real-Time profile (ARMv7-R)
    • Protected memory (MPU)
    • low latency and predictability suited for 'real-time' requirements
    • evolutionary path for traditinal embedded business
    • for example Cortex-R4
  • Microcontroller profile (ARMv7-M, ARMv7E-M, ARMv6-M)
    • lowest gate count entry point
    • deterministic and predictable behaviour a key priority
    • deeply embedded use
    • for example Cortex-M3

 

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What are possible instruction sets implemented on an ARM processor?

  • ARM instruction set are 32-bits long
  • Thumb instructions are a mix of 16-bit and 32-bit instructions 
  • VFP instruction set are 32-bit vector floating point instructions
  • NEON instruction set provides 32-bit SIMD instructions
  • Jazelle-DBX instructions provide acceleration for Java VMs
  • Jazelle-RCT provides support for interpreted languages (Lua, Swift, Python)
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What is a Load / Store architecture?

Load/Store-architectures are computer architectures which only allow meory access through two types of instructions, namely load and store instructions. If there's a need to operate upon data in memory it must be fetched from memory first and loaded into a register. Operations are done over register contents and the result can then be written back via a store instruction. Intermediate results thus have to be saved in the register file. Whereas this is classic to RISC-architectures, CISC-architectures allow direct memory accesses for ALU operations.

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How are subroutine calls handled on an ARM processor?

Subroutine calls require two steps on an ARM architecture:

  • store the current pc, i.e. the return address
  • branch to the address of the required subroutine

Both steps are carried out in one instruction, where the return address is stored in the link register (lr/r14) and the branch to the target address takes place. Returning means branching to the address stored in lr.

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What is ARM NEON?

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NEON is a wide SIMD data processing architecture

  • extension to the ARM instruction set (v7-A)
  • 32 x 64-bit registers (can be used as 16 x 128-bit as well)
  • registers are considered as vectors of elements of the same data type with data type being user defined
  • can lead to performance increase in certain applications
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What's the memory hierarchy on an ARM processor?

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The ARM memory architecture can have a memory hierarchy with several memory elements. Closest to the core there is the L1-Cache, which consits of an instruction- and a data-cache. Level-2 memory systems and beyond depends on the system design. L2-Cache and keeps the data coherent to the on-cihp memory unit, typically a SRAM. L3-Cache typicall belongs to an off-chip memory.

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State the main features of the Cortex-M0 and why it would be suitable for embedded applicatons.

The Cortex-M0 is a microcontroller from ARM built on the ARMv-6M architecture. It has a 3-stage pipeline and builds on the von Neuman architecture. The benefits are simplicity as it allows entire programming of the chip in a higher-level programming language such as C. It is the core with the smallest footprint of the ARM family and results in very low power, which is important for embedded applications.