Lernkarten

Subhan Waizi
Karten 38 Karten
Lernende 2 Lernende
Sprache English
Stufe Grundschule
Erstellt / Aktualisiert 12.05.2016 / 16.06.2017
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0 Exakte Antworten 38 Text Antworten 0 Multiple Choice Antworten
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What are control hazards? How can they be solved?

Control hazards can occur when a wront fetch decision results in a new instruction fetch and the pipeline being flushed. Dealing with these hazards is difficult in terms of resources, as they require substantial hardware overhead. Some solutions might be:

  • multiple pipeline streams
  • prefetch branch target
  • use of loop buffer
  • branch prediction
  • delayed branch
  • reordering of instructions
  • multiple copies of registers (backups)

 

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What are the main features of RISC-V?

The RISC-V is a recent architecture that originated at the University of California, Berkley. The architecture comes with many advantages, that seems to have borrowed the good features of other known architectures:

  • Small CPU that can have 16 regiters and 33 instructions for the basic version
  • ideas borrowed from SPARC, e.g. register 0 is constant and instruction register makes it a simple two-stage fetch-and-execute pipeline
  • ideas borrowed from MIPS include the missing of a status register, evaluation of branch conditions on the same cycle and memory mapped I/O-ports
  • novel ideas:
    • ALU lacks condition codes and branch conditions evaluated by seperate logic, which however makes multiple precision arithmetic complex due to lack of carry bit. Furthermore most arithmetic errors are not flagged or errored with the RISC V architecture
    • Extra space reserved for new instructions, future extensions but also user defined instructions
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What are different established types of inter-processor communication?

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  • Many CPU share a common shared memory
  • processors are connected via some sort of interconnect, however every CPU has its own local processor
  • processor + memory couple has access to internet and communicates through internet

 

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What are possible interconnect topologies for processors?

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See figure

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Explain the principles of caches.
 

Caches is a type of memory tightly coupled to the processor. It main aim is to reduce the average memory access time for processors by holding relevant copies of the main memory that can be accessed fast. When an instruction accesses data in the memory and this data can be found in the cache because it has been stored into the cache at some earlier point, it is considered as a cache hit and the processor can access the data fast. When the data cannot be found in the cache, it is considered as a cache miss and the data has to be accessed in the main memory. A cache coherence problem occurs when data in main memory is changed while the copy in the cache remains the same. In this case reading the value from the cache would result in a wrong and outdated value. Thus in terms of processor communication there has to be a mechanism that detects this and acts accordingly.

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What is considered as the cache coherence problem? What is a coherent memory scheme?

  • in shared memory multiprocessor systems, all processors share common memory
  • each processor may have local memory, part of which may be a cache system
  • same information may reside in a number of copies in some caches and main memory
  • however these multiple copies have to be kept identical so all processors work on / read the same expected data
  • this requirement imposes a cache coherence problem

A memory scheme is coherent if the value returned on a load instruction is always the value given by the latest store instruction with the same address