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Subhan Waizi
Karten 38 Karten
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Sprache English
Stufe Grundschule
Erstellt / Aktualisiert 12.05.2016 / 16.06.2017
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0 Exakte Antworten 38 Text Antworten 0 Multiple Choice Antworten
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What are problems of standard many-core approaches?

  • many-core systems with hundres of cores take too much space on SoC
  • energy and performance overhead
    • huge number of wires for inter-processor communication --> energy
    • complex switching --> large space and energy
  • parallel programming techniques not fully established and used yet
  • many programming paradigms are serial by nature not taking advantage of multi-core systems
  • aim for backward-compatibility of software
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What are the advantages of the picoMIPS architecture?

  • uses a variable-architecture application-specific design methodology that is oriented towards extremely low energy consumption, small footpring making it suited for embedded applications
  • easily extendable into an application-specific many-core environment
  • extreme energy savings in ASIC implementations and further energy techniques such as near-trheshold design, dynamic voltage and frequency scaling can be used
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Draw the block diagram of a sequential unsigned multiplier.

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What is the difference between hard cores and soft cores?

Processor cores can be classified into soft cores and hard cores

  • a hard core is an embedded process, for example ARM M0, surrounded by FPGA's memory and programmable logic
  • a soft core is synthesized from HDL code using standard FPGA's memory and logic
  • hardcores are less configurable and flexible, however provide higher performance due to optimized synthesis, layout, routing and other technologies
  • soft cores allow more configuration and customization of the processor parameters, they are however slower and often consume more power

 

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Compare some soft core processors.

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State the main features of the Altera NIOS II Soft core

  • general purpose RISC with Harvard architecture
  • 32-bit instruction set architecture with 32 GP registers
  • performance of up to 150 DMIPS on stratix family FPGA
  • three versions: economy, standard and fast core with different number of pipeline stages, instruction and data chaches and other hardware components and implementations vary in size and performance
  • peripherals addable through the Avalon Interface Bus

 

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What's the benefit of pipelining? What kind of hazards can occur in a pipelined system?

A n-staged pipeline has n-1 pipeline registers in between the hardware blocks. The benefits one can get from a pipelined setup is a speed increase of around n. In practice the speed increase will not be as high as this theoretical value, mainly due to pipeline hazards. There are mainly three different types of pipeline hazards:

  • resource hazard occurs when an instruction needs a resource being used by another instruction
  • Data hazards can be classified into a number of sub-data hazards, for example
    • RAW means a read is requested before a write has finished
    • WAR means a write is requested before a read has finished
    • WAW means that a writes occur in an uninteded order
  • Control hazards can happen when a wrong fetch decision at a branch occurs that can result in an extra instruction fetch and pipeline flush

 

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Write an example for a data access / data dependency hazard. What are solutions for solving this kind of hazard?
 

Software solutions:

  • compiler puts no-op instructions after each instruction that may cause a hazard
  • instruction scheduling, i.e. code rearranging to reduce the nr. of no-ops

Hardware solutions:

  • hazard detection and solving hardware
  • pipeline interlocking / stalling for one or more clock cycles
  • Mainly two types of data forwarding
    • ALU result of instr1 can be directly forwarded to ALU input for instr2
    • Data from a memory load in the MEM stage can be directed to ALU input
  • forwarding with interlocking 
    • assuming instr2 is data dependent on a load instr1, then instr2 has to be stalled until the data loaded by instr1 becomes available